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pe44820 document category: product specification ultracmos? rf digital phas e shifter 8-bit, 1.7C2.2 ghz ?2015, peregrine semiconductor corporation. all rights reserved. ? headquarters: 9380 carroll park drive, san diego, ca, 92121 product specification doc-43214-5 C (11/2015) www.psemi.com features ? 8-bit full-range phase shifter of 358.6; 180, 90, 45, 22.5, 11.2, 5.6, 2.8 and 1.4 bits ? low rms phase and amplitude error ? rms phase error of 1.0 ? rms amplitude error of 0.1 db ? high linearity of +60 dbm iip3 ? extended narrow band frequency operation of 1.1?3.0 ghz ? +105 c operating temperature ? packaging ? 32-lead 5 5 0.85 mm qfn applications ? base station transceivers ? weather and military radar ? active antenna arrays product description the pe44820 is a harp? technology-enhanced 8-bit digital phase shifter (dps) designed for use in a broad range of applications including: beamforming networks, distributed antenna systems, active antenna systems and phased array applications. this dps covers a phase range of 358.6 degrees in 1.4 degree steps, maintaining excellent phase and amplitude accuracy across the nominal frequency band of 1.7?2.2 ghz. the pe44820 is also capable of extended frequency operation from 1.1?3.0 ghz for narrow band applications, as detailed in application note 45. an integrated digita l control interface supports both serial and parallel programming of the phase setting. the pe44820 also featur es an external negative supply option for a faster switching frequency, and is offered in a 32-lead 5 5 0.85 mm qfn package. in addition, no external blocking capacitors are required if 0 vdc is present on the rf ports. the pe44820 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate. peregrine?s harp technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos process, offe ring the performance of gaas with the economy and integration of conventional cmos. figure 1 ? pe44820 functional diagram rf1 90 180 45 22.5 11.2 5.6 2.8 1.4 rf2 v dd v ss_ext gnd leo clko sdo1 sdo2 s/p s/p = serial s/p = parallel opt p0... p7 parallel interface a0... a3 serial address serial interface si clk le digital interface 8 4
pe44820 digital phase shifter page 2 doc-43214-5 C (11/2015) www.psemi.com optional external v ss for proper operation, the v ss_ext pin must be grounded or tied to the v ss voltage specified in table 2 . when the v ss_ext pin is grounded, fets in the switch are biased with an internal negative voltage generator. for applica- tions that require the lowest possible spur performance, v ss_ext can be applied externally to bypass the internal negative voltage generator. absolute maximum ratings exceeding absolute maximum ratings listed in table 1 may cause permanent damage. operation should be restricted to the limits in table 2 . operation between operating range maximum and absolute maximum for extended periods may reduce reliability. esd precautions when handling this ultracmos device, observe the same precautions as with any other esd-sensitive devices. although this device contains circuitry to protect it fr om damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 1 . latch-up immunity unlike conventional cmos devices, ultracmos devices are immune to latch-up. table 1 ? absolute maximum ratings for pe44820 parameter/condition min max unit supply voltage, v dd ?0.3 5.5 v negative supply voltage, v ss_ext ?3.6 ?2.4 v digital input voltage ?0.3 3.6 v maximum input power 28 dbm storage temperature range ?65 +150 c esd voltage hbm, all pins (*) 500 v note: * human body model (mil-std 883 method 3015).
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 3 www.psemi.com recommended operating conditions table 2 lists the recommended operating conditions for the pe44820. devices should not be operated outside the recommended operating conditions listed below. table 2 ? recommended operating conditions for pe44820 parameter min typ max unit normal mode, v ss_ext = 0v (1) supply voltage, v dd 2.3 5.5 v supply current, i dd 130 200 a bypass mode, v ss_ext = ?3.3v (2) supply voltage, v dd 3.3 5.5 v supply current, i dd 50 80 a negative supply voltage, v ss_ext ?3.6 ?3.2 v negative supply current, i ss ?40 ?16 a normal or bypass mode digital input high 1.17 3.6 v digital input low ?0.3 0.6 v digital input current 15 a digital input current, d4?d7 (3) 200 a rf input power, cw 25 dbm operating temperature range ?40 +25 +105 c notes: 1) normal mode: connect v ss_ext (pin 20) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. 2) bypass mode: use v ss_ext (pin 20) to bypass and disable internal negative voltage generator. 3) typical current draw 200 a @ 3.6v. recommended operation at 1.8v reduces input current draw to 0.6 a.
pe44820 digital phase shifter page 4 doc-43214-5 C (11/2015) www.psemi.com electrical specifications table 3 provides the pe44820 key electrical specifications at +25 c (z s = z l = 50 ? ), unless otherwise specified. normal mode (1) is at v dd = 3.3v and v ss_ext = 0v. bypass mode (2) is at v dd = 3.3v and v ss_ext = ?3.3v. table 3 ? pe44820 electrical specifications parameter condition min typ max unit operating frequency 1.71.952.2ghz phase shift range lsb = 1.4 +0 358.6 deg number of bits 8bits insertion loss across all states 6 7.1 db rms phase error over all 256 states 1.0 deg rms amplitude error over all 256 states 0.1 db phase accuracy across all states 3 deg attenuation variation across all states 0.50 db phase accuracy relative to reference phase @ 1.95 ghz 1.4 bit ?0.60 deg 2.8 bit ?0.40 deg 5.6 bit +0.05 deg 11.2 bit +0.25 deg 22.5 bit +0.50 deg 45 bit +0.25 deg 90 bit +1.75 deg 180 bit ?0.65 deg return loss 13 db input 0.1db compression point (3) 28 dbm input ip3 60 dbm settling time (4) rf settled within 2 deg of final value 365 ns notes: 1) normal mode: single external positive supply used. 2) bypass mode: both external positive s upply and external negative supply used. 3) the input p0.1db compression point is a linearity figure of merit. refer to table 2 for the operating rf input power (50 ? ). 4) use of v ss_ext reduces the settling time.
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 5 www.psemi.com switching frequency the pe44820 has a maximum 25 khz switching frequency in normal mode (pin 20 tied to ground). a faster switching frequency is available in bypass mode (pin 20 tied to v ss_ext ). switching frequency describes the time duration between switching events. switching time is the time between the point the control signal le reaches 50% of its final value and the point the rf output signal reaches within 10% or 90% of its target value. control logic table 4 and table 5 provide the serial/parallel selection truth table and the serial and parallel truth table for the pe44820. table 4 ? serial/parallel selection truth table for pe44820 s/ p pin control mode l parallel hs e r i a l table 5 ? serial and parallel truth table (*) phase control setting phase shift setting rf1?rf2 d0 d1 d2 d3 d4 d5 d6 d7 opt l l l l l l l l l reference phase h l l l l l l l l 1.4 deg lh l l l l l l l 2.8 deg l lh l l l l l l 5.6 deg l l lh l l l l l 11.2 deg l l l lh l l l l 22.5 deg l l l l lh l l l 45 deg l l l l l lh l h 90 deg l l l l l l lh l 180 deg hhhhhhhhh 358.6 deg l l l l l l l l h 1.4 deg note: * normal mode operation uses the opt bit to synchronize the 90 degree bi t optimizing the phase accuracy across all states. for ad ditional infor- mation on the opt bit, reference application note 45.
pe44820 digital phase shifter page 6 doc-43214-5 C (11/2015) www.psemi.com figure 2 ? serial control register map figure 3 ? buffered sdo1 serial interface phase setting word lsb (first in) msb (last in) si sdo2 sdo1 q5 q6 q7 q8 q9 q10 q11 q12 d6 d5 d4 d7 opt a0 a1 a2 a3 q0 q1 q2 q3 q4 d0 d1 d2 d3 unit address word 205.3 (256 states / 360) = state 146 state 146 01001001 lsbmsb (205.3 deg setting = 2.8 + 22.5 + 180) program wor d (lsbmsb): 01001001 0 + 1100 , opt bit is synchronized to 90 bit phase setting word is derived directly from the phase setting. for example, to program the 205.3 degree setting at unit address 3: unit address word: 1100 (unit address = 1 + 2) phase setting word: multiply the degree desired by 256 states divided by 360 and convert to binary clk si sdo1 register data note: sdo1 data buffered with respect to si and valid on rising edge of clk le d0 d1 d2 d3 opt d5 d6 d7 d4 a0 a1 a2 a3 d0 d1 d2 d3 opt d5 d6 d7 d4 a0 a1 a2 a3 t ov t sclk t su t h t sclkh t lclkh t settle t oh default/current value new value t sclkl
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 7 www.psemi.com figure 4 ? sdo2 (last bit of shift regist er)single write with readback clk si sdo2 register data note: sdo2 data is valid on the falling edge of sclk le t ov t sclk t su t h t sclkh t settle t oh default/current value new value t sclkl d0 d1 d2 d3 opt d5 d6 d7 d4 a0 a1 a2 a3 d0 d1 d2 d3 opt d5 d6 d7 d4 a0 a1 a2 a3 d0 d1 d2 d3 opt d5 d6 d7 d4 a0 a1 a2 a3 d0 d1 d2 d3 opt d5 d6 d7 d4 a0 a1 a2 a3 table 6 ? latch and clock specifications latch enable shift clock function 0 shift register clocked contents of shift register transferred to phase shifter core
pe44820 digital phase shifter page 8 doc-43214-5 C (11/2015) www.psemi.com typical performance data figure 5 ? figure 18 show the typical performance data at +25 c, v dd = 3.3v and v ss_ext = 0v, unless otherwise specified. figure 5 ? relative phase error: opt bit -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: opt bit 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz]
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 9 www.psemi.com figure 6 ? relative phase error: 180 deg bit figure 7 ? relative phase error: 90 deg bit -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 180 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz] -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 90 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz]
pe44820 digital phase shifter page 10 doc-43214-5 C (11/2015) www.psemi.com figure 8 ? relative phase error: 45 deg bit figure 9 ? relative phase error: 22.5 deg bit -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 45 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz] -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 22.5 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz]
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 11 www.psemi.com figure 10 ? relative phase error: 11.25 deg bit figure 11 ? relative phase error: 5.6 deg bit -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 11.25 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz] -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 5.6 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz]
pe44820 digital phase shifter page 12 doc-43214-5 C (11/2015) www.psemi.com figure 12 ? relative phase error: 2.8 deg bit figure 13 ? relative phase error: 1.4 deg bit -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 2.8 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz] -5 -4 -3 -2 -1 0 1 2 3 4 5 [deg] phase error: 1.4 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 frequency [mhz]
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 13 www.psemi.com figure 14 ? rms amplitude error 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 [db] -40 c 25 c 85 c 105 c frequency [mhz] 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 figure 15 ? rms phase error 0 0.5 1 1.5 2 2.5 3 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 [deg] frequency [mhz] -40c 25c 85c 105c
pe44820 digital phase shifter page 14 doc-43214-5 C (11/2015) www.psemi.com figure 16 ? maximum return loss s11 over all major states figure 17 ? maximum return loss s22 over all major states -50 -45 -40 -35 -30 -25 -20 -15 -10 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 [db] frequency [mhz] -40 c 25 c 85 c 105 c -50 -45 -40 -35 -30 -25 -20 -15 -10 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 [db] frequency [mhz] -40 c 25 c 85 c 105 c
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 15 www.psemi.com figure 18 ? insertion lossreference states -9 -8.5 -8 -7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 [db] frequency [mhz] -40 c 25 c 85 c 105 c
pe44820 digital phase shifter page 16 doc-43214-5 C (11/2015) www.psemi.com evaluation kit the pe44820 evaluation kit (evk) incl udes hardware required to control and evaluate the functionality of the dps. the dps evaluation software can be downloaded at www.psemi.com and requires a pc running windows ? operating system to control the usb interface b oard. refer to the pe44820 evaluation kit user?s manual for more information. figure 19 ? evaluation kit layout for pe44820
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 17 www.psemi.com pin information this section provides pinout information for the pe44820. figure 20 shows the pin map of this device for the available package. table 7 provides a description for each pin. figure 20 ? pin configuration (top view) table 7 ? pin descriptions for pe44820 pin no. pin name description 1 opt (1) phase accuracy optimization bit. 2 v dd supply voltage. 3s/ p serial/parallel mode select. 4?6, 8?17, 19, 21 gnd ground. 7 rf1 (2) rf1 port. 18 rf2 (2) rf2 port exposed ground pad si d5/clk0 d6/sdo1 d7/sdo2 gnd gnd gnd d3/a3 d2/a2 d1/a1 d0/a0 gnd gnd gnd le gnd v ss_ext gnd rf2 gnd gnd clk opt s/p gnd gnd gnd rf1 gnd v dd 1 3 4 5 6 7 8 2 9 11 12 13 14 15 16 10 32 30 29 28 27 26 25 31 24 22 21 20 19 18 17 23 d4/le0 gnd pin 1 dot marking 20 v ss_ext (3) external v ss negative supply voltage. 22 le serial interface latch enable input. 23 clk serial interface clock input. 24 si serial interface data input. 25 d7/sdo2 (4)(6) parallel?d7 180 bit/serial data out 2. 26 d6/sdo1 (4)(6) parallel?d6 90 bit/serial data out 1. 27 d5/clk0 (6) parallel?d5 45 bit/serial-buff- ered clk out. 28 d4/le0 (6) parallel?d4 22.4 bit/serial buff- ered le out. 29 d3/a3 parallel?d3 11.2 bit/serial a3 address bit. 30 d2/a2 parallel?d2 5.6 bit/serial a2 address bit. 31 d1/a1 parallel?d1 2.8 bit/serial a1 address bit. 32 d0/a0 parallel?d0 1.4 bit/serial a0 address bit. pad gnd exposed pad: ground for proper operation. notes: 1) opt bit is used to optimize the phase accuracy across all states. opt bit (pin 1) must be synchronized to the 90 bit (pin 26) for normal operation. 2) rf1 and rf2 (pins 7 and 18) are bi-directional. 3) use v ss_ext (pin 20) with negative supply (v ss_ext = ?3.6v) to bypass and disable internal negative voltage generator. connect v ss_ext (pin 20) to gnd (v ss_ext = 0v) to enable internal neg- ative voltage generator. 4) sdo2 is buffered output of the last bit of the internal shift register. 5) sdo1 is a buffered output of the serial data input. 6) d4?d7 (pins 25?28) are bi-directional pins. table 7 ? pin descriptions for pe44820 (cont.) pin no. pin name description
pe44820 digital phase shifter page 18 doc-43214-5 C (11/2015) www.psemi.com packaging information this section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape and reel information. moisture sensitivity level the moisture sensitivity level rating for the pe44820 in the 32-lead 5 5 0.85 mm qfn package is msl1. package drawing top-marking specification figure 21 ? package mechanical drawing for 32-lead 5 5 0.85 mm qfn figure 22 ? package marking specifications for pe44820 top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 5.00 5.00 0.400.05 (x32) 3.600.05 0.250.05 (x32) 0.50 3.50 ref 3.600.05 0.850.05 0.05 ref 0.203 ref (x28) 0.30 (x32) 0.60 (x32) 3.65 3.65 5.40 5.40 0.50 (x28) 1 8 9 32 17 24 25 16 = yy = ww = zzzzzzz = pin 1 indicator last two digits of assembly year assembly work week assembly lot code (maximum seven characters) 44820 yyww zzzzzzz
pe44820 digital phase shifter doc-43214-5 C (11/2015) page 19 www.psemi.com tape and reel specification figure 23 ? tape and reel specifications for 32-lead 5 5 0.85 mm qfn device orientation in tape pin 1 t k0 a0 b0 p0 p1 d1 a section a-a a direction of feed d0 e w0 p2 see note 3 see note 1 f see note 3 a0 b0 k0 d0 d1 e f p0 p1 p2 t w0 5.25 5.25 1.10 1.50 + 0.1/ -0.0 1.5 min 1.75 0.10 5.50 0.05 4.00 8.00 2.00 0.05 0.30 0.05 12.00 0.30 notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole dimensions are in millimeters unless otherwise specified
pe44820 digital phase shifter product specification www.psemi.com doc-43214-5 C (11/2015) document categories advance information the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the datasheet contains final data. in the event peregrine decides to change the specifications, peregri ne will notify customers of the intended changes by issuing a cnf (customer notification form). product brief this document contains a shortened version of the datasheet. for the full datasheet, contact sales@psemi.com. not recommended for new designs (nrnd) this product is in production but is not recommended for new designs. end of life (eol) this product is currently going th rough the eol process. it has a specific last-time buy date. obsolete this product is discontinued. orde rs are no longer accepted for this product. sales contact for additional information, contact sales at sales@psemi.com. disclaimers the information in this document is believed to be reliable. ho wever, peregrine assumes no liability for the use of this inform ation. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this document are implied or granted to any third party. peregrine?s products are not designed or intended for use in devi ces or systems intended for surgical implant, or in other appl ications intended to support or sustain life, or in any applicati on in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, incl uding consequential or incidental damages, aris ing out of the use of its products in such applications. patent statement peregrine products are protected under one or more of the following u.s. patents: patents.psemi.com copyright and trademark ?2015, peregrine semiconductor corporation. all rights reserved. the peregrine name, l ogo, utsi and ultracmo s are registered tr ademarks and harp, multiswitch and dune are trademar ks of peregrine semiconductor corp. ordering information table 8 lists the available ordering codes for the pe44820 as well as available shipping methods. table 8 ? order codes for pe44820 order codes description packaging shipping method pe44820a?x pe44820 digital phase shifter green 32-lead 5 5 mm qfn 500 units/t&r ek44820?01 pe44820 evaluation kit evaluation kit 1/box

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